Investor Presentaiton

Services Offered PHYSICAL DESIGN / SYNTHESIS/ ANALOG LAYOUT DESIGN VERIFICATION DFT / TIMING MOSCHIP ☐ 800 + VLSI Engineers Hours Delivered 3.0+ Million Engineering ☐ 100+ ASIC tape-outs with ☐ 100% first pass silicon success Engagement Model: ODC | T&M | Turnkey ■ Achieved "first-pass silicon success" across 100+ ASIC tape outs Expertise ranging from 500nm to the latest 5/6/7/10/14/16 nm FinFET & SOI process nodes Very strong RTL Design, Design Verification, Physical Design, Analog Design, and Analog Layout team with over 15 years of average experience in the senior team Engaged in complex chip designs extending to 100+ million gates Highest level of training & experience on state-of-the-art technologies 7

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