Corporate Overview for Investors

3DIC Compiler: Unified Exploration-to-Signoff Platform 3DIC COMPILER PLATFORM Architectural Planning Abstraction, Visualization 2.5D/3D Prototyping Early Analysis What-if Evaluation Design Creation Die Partitions Floorplaning Connectivity Planning Implementability Checks In-design Co-Analysis Design Implementation Power, Clock Delivery D2D Routing Multi-die DFT Custom Router In-design Co-analysis 4 Signoff / System Analysis DRC/ LVS Extract STA Power Thermal COMMON FUSION DATA MODEL EMIR SI/PI Synopsys® 2.5D Interposer, RDL Fanout, 3D Stacked Designs м Synopsys Confidential Information Highly Integrated, Scalable Platform System-of-chips integration over 100s of Billions of transistors Leveraging common data-model & tech files for 2D and 3D designs Flexible, Efficient Workflow Environment Fast exploration and pathfinding to accelerate 3D design creation and D2D planning Comprehensive Design and Closure Full breadth of high-throughput engines - Digital, custom, auto D2D routing, native DRC, DFT, ECO and more Trusted, Golden Signoff Analysis Integrated industry standard technologies for convergence to optimal PPA/mm³ – incl. STA, Thermal, EMIR, SI/PI 2022 Synopsys, Inc. 27

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