AMD Investor Day Presentation Deck

AMD XDNA: ADAPTIVE ARCHITECTURE IP ▪ Dataflow architecture optimal for Al and signal processing applications Highly-scalable array of engines with local memory and data movers Leverages deep expertise of compiling algorithms to FPGAs and adaptive SoCs Adaptive Interconnect AI Engine AI Engine Al Engine (AIE) AI Engine Local Mem. Local Mem. Local Mem. AI Engine AI Engine Local Mem. Local Mem. Local AI Engine Mem. Source: The McClean Report, May 2022 High-Performance and Energy Efficiency for Al and Signal Processing FPGA LOGIC Adaptive Interconnect FPGA LOGIC FPGA Fabric FPGA LOGIC (FPGA) Local Mem. Local Mem. Local Mem. FPGA LOGIC FPGA LOGIC FPGA LOGIC Local Mem. Local Mem. Local Mem. Leading FPGA for broad set of applications and Al

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