Corporate Overview for Investors

Enabling and Leveraging the Potential of Al Design and Verification Tools for Al Processors Multiple years of collaboration alongside Al pioneers - deep understanding of Al design implications and challenges Verification solutions from architecture to simulation to emulation and prototyping Digital Design Family significantly enhanced to address Al processor design challenges synopsys® Al Processor Key Design Solutions - Data Center Lessons learnt working with Al technology pioneers DESIGN CHALLENGE Capacity, turnaround time 100s of MIM/MIBs, many power domains. Signal routing congestion Transistor-dominated layout, congestion, macro timing path closure EM effects, parasitics, inductance AUTO RE-ARCHITECTURE, PLACEMENT Clock vs. data path power optimization Ince 24.19% IR drop issues, need for robust power grid Wire Al Processor Key Design Solutions - Data Center . Sparse logic, low utilization areas © 2018 Spot the 21 Al Accelerator Par Synopsys Confidential Information Lessons learnt working with Al technology pioneers DESIGN CHALLENGE Capacity, turnaround time 100s of MIM/MIBS, many power domains, abutted FPs, hierarchy, global clocking Signal routing congestion Clock routing through dense PG structures Transistor-dominated layout, congestion, macro timing path closure EM effects, parasitics, inductance Clock vs. data path power optimization IR drop issues, need for robust power d Sparse logic, low utilization areas MAXIMIZATION OF FEED-THROUGH RE-USE Handling of Complex Star Connections Ensuring Feedthrough Reusability for MIBs Maximize Net-Bundle "Togetherness" Clock-Domain-Aware Dealing with Custom Tracks Enabling Efficient Clock Station Management Pin Placement Recent Al Processor Tape-out Al Processor Key Design Solutions - Edge Lessons learnt working with Al technology pioneers ©2018 S2 DESIGN CHALLENGE GHz+ timing closure challenges; variability floorplan exploration, channel congestion Macro-dominated layout, congestion, dense routing Memory placement and continuous core area for cell placement " Aggressive CNN engine power optimization Switching power, clock network ⚫ DRAM if power considerations ⚫ I/O pin constraints ECO FUSION TECHNOLOGY Up to 40% Faster TTR to Signoff 97 scen for signoff, 25 scen for implementation Baseline Flow route opt PT&ICC2 PT Manual ECOs ECO Fusion Flow Reduced ECO route opt Fusion ICC2 PT route opt ECO Fusion 4ECOs. Signoff 030 vs inc 4 30% Faster Synopsys 2022 Synopsys, Inc. 11

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